Design Challenges for High Performance Nano-Technology

This tutorial present the key aspects of design challenges and its solutions that are being experienced in VLSI design in the era of nano technology. The focus will be on design challenges that are experienced in microprocessor designs. It will capture the design issues in the areas of high level architectural modeling, design for manufacturability (DFM), layout synthesis, standard cell design, and performance verification. It will describe the requirements to meet power, timing, physical dimension and process portability goals with nano-technology. It will also address the pre and post silicon verification difficulties that have a direct impact on taking the product to market. This tutorial covers the following main topics in detail: • Expectation from the VLSI product (Moore’s law, Higher performance, higher clock speed, smaller die, lower dynamic and static power, higher reliability) • High level Modeling Challenges that includes power modeling, performance analysis, DFT and HVM modeling and RTL esitmation of key design metrics. • Design-for-Manufacturability (DFM) challenges; Nano process physical design, extraction, reliability. • Design-for-Test challenges that addresses DFT strategy and planning, Fault models, Full/partial scan design, and special test structures. • Performance verification that describes the limitation of static timing model, affect of small devices, higher temperature impact from a dense area, voltage drop due to on die variation, etc. • Standard cell library usage and design is critical to achieve higher Fmax. It will address standard cell layout architecture, granularity of library strength, parameterized cells. • Layout synthesis using congestion minimization process, intelligent partitioning and clock tree synthesis for high density design. • Post silicon debugging and process correlation; Special circuit verification, power budget verification, process correlation issues, DPM prediction, reliability verification and Burn-in